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MCP4921/4922
12-Bit DAC with SPITM Interface
Features
* * * * * * * * * * * * * 12-Bit Resolution 0.2 LSB DNL (typ) 2 LSB INL (typ) Single or Dual Channel Rail-to-Rail Output SPITM Interface with 20 MHz Clock Support Simultaneous Latching of the Dual DACs w/LDAC Fast Settling Time of 4.5 s Selectable Unity or 2x Gain Output 450 kHz Multiplier Mode External VREF Input 2.7V to 5.5V Single-Supply Operation Extended Temperature Range: -40C to +125C
Description
The Microchip Technology Inc. MCP492X are 2.7 - 5.5V, low-power, low DNL, 12-Bit Digital-to-Analog Converters (DACs) with optional 2x buffered output and SPI interface. The MCP492X are DACs that provide high accuracy and low noise performance for industrial applications where calibration or compensation of signals (such as temperature, pressure and humidity) are required. The MCP492X are available in the extended temperature range and PDIP, SOIC, MSOP and TSSOP packages. The MCP492X devices utilize a resistive string architecture, with its inherent advantages of low DNL error, low ratio metric temperature coefficient and fast settling time. These devices are specified over the extended temperature range. The MCP492X include doublebuffered inputs, allowing simultaneous updates using the LDAC pin. These devices also incorporate a Power-On Reset (POR) circuit to ensure reliable power-up.
Applications
* * * * * Set Point or Offset Trimming Sensor Calibration Digitally-Controlled Multiplier/Divider Portable Instrumentation (Battery-Powered) Motor Feedback Loop Control
Package Types
8-Pin PDIP, SOIC, MSOP
VDD 1
Block Diagram
CS SDI SCK LDAC
8 VOUTA 7 AVSS 6 VREFA 5 LDAC
MCP4921
CS 2
VDD
SCK 3 SDI 4
Interface Logic
Power-on Reset
AVSS Input Input Register A Register B DACA Register VREF A String DACA Buffer Gain Logic Output Op Amps Output Logic String DACB Buffer Gain Logic DACB Register VREF B
14-Pin PDIP, SOIC, TSSOP
VDD 1 NC 2 CS 3 SCK 4 SDI 5 NC 6 NC 7
14 VOUTA 13 VREFA 12 AVSS 11 VREFB 10 VOUTB 9 SHDN 8 LDAC
MCP4922
VOUTA
SHDN
VOUTB
2004 Microchip Technology Inc.
DS21897A-page 1
MCP4921/4922
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
VDD ............................................................................................................. 6.5V All inputs and outputs w.r.t ............. AVSS -0.3V to VDD+0.3V Current at Input Pins ....................................................2 mA Current at Supply Pins ...............................................50 mA Current at Output Pins ...............................................25 mA Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-55C to +125C ESD protection on all pins ........... 4 kV (HBM), 400V (MM) Maximum Junction Temperature (TJ) . .........................+150C
5V AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85C. Typical values at +25C. Parameters Power Requirements Input Voltage Input Current - MCP4921 Input Current - MCP4922 Hardware Shutdown Current Software Shutdown Current Power-on-Reset Threshold DC Accuracy Resolution INL Error DNL Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Input Amplifier (VREF Input) Input Range - Buffered Mode Input Range - Unbuffered Mode Input Impedance Input Capacitance Unbuffered Mode Multiplier Mode -3 dB Bandwidth VREF VREF RVREF CVREF fVREF fVREF Multiplier Mode Total Harmonic Distortion Note 1: 2: THDVREF 0.040 0 -- -- -- -- -- -- -- 165 7 450 400 -73 VDD - 0.040 VDD -- -- -- -- -- V V k pF kHz kHz dB VREF = 2.5V 0.2Vp-p, Unbuffered, G=1 VREF = 2.5V 0.2 Vp-p, Unbuffered, G=2 VREF = 2.5V 0.2Vp-p, Frequency = 1 kHz Note 1 Code = 2048 VREF = 0.2v p-p, f = 100 Hz and 1 kHz Unbuffered Mode n INL DNL VOS VOS/C gE 12 -12 -0.75 -- -- -- -- -- -- 2 0.2 0.02 0.16 -0.44 -0.10 -3 -- 12 +0.75 1 -- -- 1 -- Bits LSB LSB ppm/C ppm/C Device is Monotonic -45C to 25C +25C to 85C % of FSR Code 0x000h VDD IDD 2.7 -- -- -- -- -- -- 175 350 0.3 3.3 2.0 5.5 350 700 2 6 -- A Input unbuffered, digital inputs grounded, output unloaded, code at 0x000 Sym Min Typ Max Units Conditions
ISHDN ISHDN_SW VPOR
A A V
G/C
% of FSR Code 0xFFFh, not including offset error. ppm/C
By design, not production tested. Too small to quantify.
DS21897A-page 2
2004 Microchip Technology Inc.
MCP4921/4922
5V AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85C. Typical values at +25C. Parameters Output Amplifier Output Swing VOUT -- 0.010 to VDD - 0.040 66 0.55 15 4.5 -- Accuracy is better than 1 LSB for VOUT = 10 mV to (VDD - 40 mV) degrees V/s mA s Within 1/2 LSB of final value from 1/4 to 3/4 full-scale range Note 2 1 LSB change around major carry (0111...1111 to 1000...0000) Note 2 Note 2 Sym Min Typ Max Units Conditions
Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance DAC-to-DAC Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note 1: 2:
m
SR ISC tsettling
-- -- -- --
-- -- 24 --
-- -- -- --
10 45 10 10
-- -- -- --
nV-s nV-s nV-s nV-s
By design, not production tested. Too small to quantify.
3V AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85C. Typical values at 25C Parameters Power Requirements Input Voltage Input Current - MCP4921 Input Current - MCP4922 Hardware Shutdown Current Software Shutdown Current Power-On Reset threshold DC Accuracy Resolution INL Error DNL Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Input Amplifier (VREF Input) Input Range - Buffered Mode Input Range - Unbuffered Mode Input Impedance Note 1: 2: VREF VREF RVREF 0.040 0 -- -- -- 165 VDD-0.040 VDD -- V V k Note 1 Code = 2048, VREF = 0.2v p-p, f = 100 Hz and 1 kHz Unbuffered Mode n INL DNL VOS VOS/C gE 12 -12 -0.75 -- -- -- -- -- -- 3 0.3 0.02 0.5 -0.77 -0.15 -3 -- +12 +0.75 1 -- -- 1 -- Bits LSB LSB % of FSR ppm/C ppm/C % of FSR ppm/C Device is Monotonic Code 0x000h -45C to 25C +25C to 85C Code 0xFFFh, not including offset error. VDD IDD 2.7 -- -- -- -- -- -- 125 250 0.25 2 2.0 5.5 250 500 2 6 -- A Input unbuffered, digital inputs grounded, output unloaded, code at 0x000 Sym Min Typ Max Units Conditions
ISHDN ISHDN_SW VPOR
A A V
G/C
By design, not production tested. Too small to quantify.
2004 Microchip Technology Inc.
DS21897A-page 3
MCP4921/4922
3V AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x, RL = 5 k to GND, CL = 100 pF TA = -40 to +85C. Typical values at 25C Parameters Input Capacitance - Unbuffered Mode Multiplier Mode -3 dB Bandwidth Sym CVREF fVREF fVREF Multiplier Mode - Total Harmonic Distortion Output Amplifier Output Swing VOUT -- 0.010 to VDD - 0.040 66 0.55 14 4.5 -- Accuracy is better than 1 LSB for VOUT = 10 mV to (VDD - 40 mV) degrees V/s mA s Within 1/2 LSB of final value from 1/4 to 3/4 full-scale range Note 2 1 LSB change around major carry (0111...1111 to 1000...0000) Note 2 Note 2 THDVREF Min -- -- -- -- Typ 7 440 390 -73 Max -- -- -- -- Units pF kHz kHz dB VREF = 2.048V 0.1 Vp-p, unbuffered, G=1 VREF = 2.048V 0.1 Vp-p, unbuffered, G=2 VREF = 2.5V 0.1 Vp-p, Frequency = 1 kHz Conditions
Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance DAC-to-DAC Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note 1: 2:
m
SR ISC tsettling
-- -- -- --
-- -- 24 --
-- -- -- --
10 45 10 10
-- -- -- --
nV-s nV-s nV-s nV-s
By design, not production tested. Too small to quantify.
5V EXTENDED TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values at +125C by characterization or simulation. Parameters Power Requirements Input Voltage Input Current - MCP4921 Input Current - MCP4922 Hardware Shutdown Current Software Shutdown Current Power-On Reset threshold DC Accuracy Resolution INL Error DNL Offset Error Offset Error Temperature Coefficient Note 1: 2: n INL DNL VOS VOS/C 12 -- -- -- -- -- 4 0.25 0.02 -5 -- -- -- -- -- Bits LSB LSB % of FSR ppm/C Device is Monotonic Code 0x000h +25C to +125C VDD IDD 2.7 -- -- -- -- -- -- 200 400 1.5 5 1.85 5.5 -- -- -- -- -- A Input unbuffered, digital inputs grounded, output unloaded, code at 0x000 Sym Min Typ Max Units Conditions
ISHDN ISHDN_SW VPOR
A A V
By design, not production tested. Too small to quantify.
DS21897A-page 4
2004 Microchip Technology Inc.
MCP4921/4922
5V EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 k to GND, CL = 100 pF. Typical values at +125C by characterization or simulation. Parameters Gain Error Gain Error Temperature Coefficient Input Amplifier (VREF Input) Input Range - Buffered Mode VREF -- 0.040 to VDD0.040 -- 174 7 450 400 -- -- V Note 1 Code = 2048, VREF = 0.2v p-p, f = 100 Hz and 1 kHz Sym gE Min -- -- Typ -0.10 -3 Max -- -- Units % of FSR ppm/C Conditions Code 0xFFFh, not including offset error
G/C
Input Range - Unbuffered Mode Input Impedance Input Capacitance Unbuffered Mode Multiplying Mode -3 dB Bandwidth
VREF RVREF CVREF fVREF fVREF
0 -- -- -- -- --
VDD -- -- -- -- --
V k pF kHz kHz dB VREF = 2.5V 0.1 Vp-p, Unbuffered, G=1 VREF = 2.5V 0.1 Vp-p, Unbuffered, G=2 VREF = 2.5V 0.1Vp-p, Frequency = 1 kHz Accuracy is better than 1 LSB for VOUT = 10 mV to (VDD - 40 mV) degrees V/s mA s Within 1/2 LSB of final value from 1/4 to 3/4 full-scale range Note 2 1 LSB change around major carry (0111...1111 to 1000...0000) Note 2 Note 2 Unbuffered Mode
Multiplying Mode - Total Harmonic Distortion Output Amplifier Output Swing
THDVREF
VOUT
--
Phase Margin Slew Rate Short Circuit Current Settling Time Dynamic Performance DAC to DAC Crosstalk Major Code Transition Glitch Digital Feedthrough Analog Crosstalk Note 1: 2:
m
SR ISC tsettling
0.010 to VDD - 0.040 66 0.55 17 4.5
--
-- -- -- --
-- -- -- --
-- -- -- --
10 45 10 10
-- -- -- --
nV-s nV-s nV-s nV-s
By design, not production tested. Too small to quantify.
2004 Microchip Technology Inc.
DS21897A-page 5
MCP4921/4922
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V - 5.5V, TA= -40 to +125C. Typical values are at +25C. Parameters Schmitt Trigger High-Level Input Voltage (All digital input pins) Schmitt Trigger Low-Level Input Voltage (All digital input pins) Hysteresis of Schmitt Trigger Inputs Input Leakage Current Digital Pin Capacitance (All inputs/outputs) Clock Frequency Clock High Time Clock Low Time CS Fall to First Rising CLK Edge Data Input Setup Time Data Input Hold Time SCK Rise to CS Rise Hold Time CS High Time LDAC Pulse Width LDAC Setup Time SCK Idle Time before CS Fall Note 1: Sym VIH Min 0.7 VDD Typ -- Max -- Units V Conditions
VIL
--
--
0.2 VD
D
V
VHYS ILEAKAGE CIN, COUT FCLK tHI tLO tCSSR tSU tHD tCHS tCSH tLD tLS tIDLE
-- -1 -- -- 15 15 40 15 10 15 15 100 40 40
0.05 VDD -- 10 -- -- -- -- -- -- -- -- -- -- --
-- 1 -- 20 -- -- -- -- -- -- -- -- -- -- A pF MHz ns ns ns ns ns ns ns ns ns ns SHDN = LDAC = CS = SDI = SCK + VREF = VDD or AVSS VDD = 5.0V, TA = +25C, fcLK = 1 MHz (Note 1) TA = +25C (Note 1) Note 1 Note 1 Applies only when CS falls with CLK high. (Note 1) Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
By design and characterization, not production tested.
tCSH CS tIDLE tCSSR Mode 1,1 SCK Mode 0,0 tSU SI MSB in LSB in tHD tHI tLO tCHS
LDAC tLS tLD
FIGURE 1-1:
SPITM Input Timing.
DS21897A-page 6
2004 Microchip Technology Inc.
MCP4921/4922
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, AVSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1: JA JA JA JA JA JA -- -- -- -- -- -- 85 163 206 70 120 100 -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Note 1 Sym Min Typ Max Units Conditions
The MCP492X family of DACs operate over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of 150C.
2004 Microchip Technology Inc.
DS21897A-page 7
MCP4921/4922
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = 5V , AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
0.3 Absolute DNL (LSB) 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 0 1024 2048 Code (Decimal) 3072 4096 0.0766 0.0764 0.0762 0.076 0.0758 0.0756 0.0754 0.0752 0.075 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (C)
FIGURE 2-1:
DNL vs. Code.
FIGURE 2-4: Temperature.
0.35 Absolute DNL (LSB) 0.3 0.25 0.2 0.15 0.1 0.05 0 1 2
Absolute DNL vs. Ambient
0.2
0.1 DNL (LSB)
0
-0.1
-0.2 0 1024 2048 3072
125C 85C
4096
25C
3
4
5
Code (Decimal)
Voltage Reference (V)
FIGURE 2-2: Temperature.
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 1024
DNL vs. Code and Ambient
FIGURE 2-5: Reference.
Absolute DNL vs. Voltage
2048
1
3072
2 3 4
4096
5.5
Code (Decimal)
FIGURE 2-3: Gain=1.
DNL vs. Code and VREF.
DS21897A-page 8
2004 Microchip Technology Inc.
MCP4921/4922
Note: Unless otherwise indicated, TA = +25C, VDD = 5V , AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
5 4 3 2 1 0 -1 -2 -3 -4 -5 0 1024 2048 3 2 1 INL (LSB) 0 -1 -2 -3 -4 3072 4096 0 1024
1 2
Ambient Temperature
VREF
3 4 5.5
125C
85
25
INL (LSB)
Code (Decimal)
2048 3072 Code (Decimal)
4096
FIGURE 2-6: Temperature.
2.5 Absolute INL (LSB) 2 1.5 1 0.5 0 -40 -20 0
INL vs. Code and Ambient
FIGURE 2-9:
INL vs. Code and VREF.
2 0 INL (LSB) -2 -4 -6 20 40 60 80 100 120 0 1024 2048 Code (Decimal) 3072 4096
Ambient Temperature (C)
FIGURE 2-7: Temperature.
3
Absolute INL vs. Ambient
FIGURE 2-10:
Note:
INL vs. Code.
Single device graph (Figure 2-10) for illustration of 64 code effect.
Absolute INL (LSB)
2.5 2 1.5 1 0.5 0
1
2
3
4
5
Voltage Reference (V)
FIGURE 2-8:
Absolute INL vs. VREF.
2004 Microchip Technology Inc.
DS21897A-page 9
MCP4921/4922
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2.
210 190 IDD (A) 170 150 130 110 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
5.5V 5.0V 4.0V 3.0V 2.7V VDD
400
5.5V 5.0V 4.0V 3.0V 2.7V VDD
350 IDD (A)
300
250
200 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
FIGURE 2-11: MCP4921 IDD vs. Ambient Temperature and VDD.
18 16 14 Occurrence 12 10 8 6 4 2 0 143 145 147 149 151 153 155 157 159 161 163 165 167 IDD (A)
FIGURE 2-14: MCP4922 IDD vs. Ambient Temperature and VDD.
20 18 16 14 12 10 8 6 4 2 0 215 225 235 245 255 265 275 285 295 305 315 400 415 IDD (A) 325
FIGURE 2-12: (VDD = 2.7V).
9 8 7 Occurrence
MCP4921 IDD Histogram
Occurrence
FIGURE 2-15: (VDD = 2.7V).
16 14 12 Occurrence 10 8 6 4 2 0 250 265 280 295
MCP4922 IDD Histogram
6 5 4 3 2 1 0 151 156 161 166 171 176 181 186 191 196 201 IDD (A)
310
325
340
355
370
IDD (A)
FIGURE 2-13: (VDD = 5.0V).
MCP4921 IDD Histogram
FIGURE 2-16: (VDD = 5.0V).
MCP4922 IDD Histogram
DS21897A-page 10
2004 Microchip Technology Inc.
385
MCP4921/4922
Note: Unless otherwise indicated, TA = +25C, VDD = 5V , AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
2
5.5V
-0.08
5.0V
VDD 5.5V
Gain Error (%)
1.5 ISHDN (A)
-0.1
5.0V
1
4.0V 3.0V 2.7V
-0.12
4.0V 3.0V 2.7V
0.5
VDD
-0.14
0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
-0.16 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
FIGURE 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD.
6
5.5V
FIGURE 2-20: Gain Error vs. Ambient Temperature and VDD.
4
VDD 5.5V 5.0V
5 ISHDN_SW (A) 4 3 2
5.0V
VIN Hi Threshold (V)
3.5 3 2.5 2 1.5 1
4.0V 3.0V 2.7V VDD
4.0V
1 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
3.0V 2.7V
-40
-20
0 20 40 60 80 100 120 Ambient Temperature (C)
FIGURE 2-18: Software Shutdown Current vs. Ambient Temperature and VDD.
0.12
FIGURE 2-21: VIN High Threshold vs Ambient Temperature and VDD.
1.6 VIN Low Threshold (V) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
3.0V 2.7V 4.0V
0.1 Offset Error (%) 0.08 0.06 0.04 0.02 0 -0.02 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
5.0V 4.0V 3.0V 2.7V VDD
VDD 5.5V 5.0V
5.5V
FIGURE 2-19: Offset Error vs. Ambient Temperature and VDD.
FIGURE 2-22: VIN Low Threshold vs Ambient Temperature and VDD.
2004 Microchip Technology Inc.
DS21897A-page 11
MCP4921/4922
Note: Unless otherwise indicated, TA = +25C, VDD = 5V , AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C) 0.0045 VOUT_LOW Limit (Y-AVSS)(V) 0.004 0.0035 0.003
5.0V VDD 5.5V
VDD 5.5V 5.0V 4.0V 3.0V 2.7V
VIN_SPI Hysteresis (V)
0.0025 0.002 0.0015 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
4.0V 3.0V 2.7V
FIGURE 2-23: Input Hysteresis vs. Ambient Temperature and VDD.
175 VREF_UNBUFFERED Impedance (kOhm)
FIGURE 2-26: VOUT Low Limit vs. Ambient Temperature and VDD.
18 IOUT_HI_SHORTED (mA)
VDD 5.5V 5.0V 4.0V 3.0V 2.7V
5.5V 2.7V VDD
17 16 15 14 13 12 11 10
170
165
160
155 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
-40
-20
0 20 40 60 80 100 120 Ambient Temperature (C)
FIGURE 2-24: VREF Input Impedance vs. Ambient Temperature and VDD.
0.045 VOUT_HI Limit (VDD-Y)(V) 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (C)
5.5V 5.0V 4.0V
FIGURE 2-27: IOUT High Short vs. Ambient Temperature and VDD.
6.0 5.0
VREF=4.0
VOUT (V)
4.0
Output Shorted to VDD
3.0V 2.7V VDD
3.0 2.0 1.0 0.0 0 2 4 6 8 10 IOUT (mA) 12 14 16
Output Shorted to VSS
FIGURE 2-25: VOUT High Limit vs. Ambient Temperature and VDD.
FIGURE 2-28:
IOUT vs VOUT. Gain = 1.
DS21897A-page 12
2004 Microchip Technology Inc.
MCP4921/4922
Note: Unless otherwise indicated, TA = +25C, VDD = 5V , AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
VOUT VOUT SCK LDAC Time (1 s/div) LDAC Time (1 s/div)
FIGURE 2-29:
VOUT Rise Time 100%.
FIGURE 2-32:
VOUT Rise Time 25% - 75%
VOUT VOUT SCK SCK LDAC Time (1 s/div) LDAC Time (1 s/div)
FIGURE 2-30:
VOUT Fall Time.
FIGURE 2-33: Shutdown.
VOUT Rise Time Exit
VOUT SCK
LDAC Time (1 s/div)
Ripple Rejection (dB)
Frequency (Hz)
FIGURE 2-31:
VOUT Rise Time 50%.
FIGURE 2-34:
PSRR vs. Frequency.
2004 Microchip Technology Inc.
DS21897A-page 13
MCP4921/4922
Note: Unless otherwise indicated, TA = +25C, VDD = 5V , AVSS = 0V, VREF = 2.50V, Gain = 2, RL = 5 k, CL = 100 pF.
0
0 -2 Attenuation (dB) -4 -6 -8 -10 -12 100
D= D= D= D= D= D= D= D= D= D= D= D= D= D= D= 160 416 672 928 1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744
-45 qVREF - qVOUT
-90
-135
Frequency (kHz)
1,000
-180 100
D= D= D= D= D= D= D= D= D= D= D= D= D= D= D=
160 416 672 928 1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744
Frequency (kHz)
1,000
FIGURE 2-35:
Multiplier Mode Bandwidth.
FIGURE 2-37:
Phase Shift.
Figure 2-35 calculation: Attenuation (dB) = 20 log (VOUT/VREF) - 20 log (G(D/4096))
600 580 560 540 520 500 480 460 440 420 400
Bandwidth (kHz)
G=1 G=2
FIGURE 2-36: Codes.
DS21897A-page 14
44 37 88 34 32 32 76 29 20 27 64 24 08 22 52 19 96 16 40 14 84 11 8 92 2 67 6 41 0 16
Worst Case Codes (decimal)
-3 db Bandwidth vs. Worst
2004 Microchip Technology Inc.
MCP4921/4922
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP4921 Pin No. 1 -- 2 3 4 -- -- 5 -- -- -- 7 6 8
PIN FUNCTION TABLE
MCP4922 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VDD NC CS SCK SDI NC NC LDAC SHDN VOUTB VREFB AVSS VREFA VOUTA Function Positive Power Supply Input (2.7V to 5.5V) No Connection Chip Select Input Serial Clock Input Serial Data Input No Connection No Connection Syncronization input used to transfer DAC settings from serial latches to the output latches. Hardware Shutdown Input DACB Output DACB Voltage Input (AVSS to VDD) Analog ground DACA Voltage Input (AVSS to VDD) DACA Output
3.1
Positive Power Supply Input (VDD)
3.6
Hardware Shutdown Input (SHDN)
VDD is the positive power supply input. The input power supply is relative to AVSS and can range from 2.7V to 5.5V. A decoupling capacitor on VDD is recommended to achieve maximum performance.
SHDN is the hardware shutdown input that requires an active-low input signal to configure the DACs in their low-power Standby mode.
3.7 3.2 Chip Select (CS)
CS is the chip select input, which requires an active-low signal to enable serial clock and data functions.
DACx Outputs (VOUTA, VOUTB)
VOUTA and VOUTB are DAC outputs. The DAC output amplifier drives these pins with a range of AVSS to VDD.
3.8 3.3 Serial Clock Input (SCK)
SCK is the SPI compatible serial clock input.
DACX Voltage Reference Inputs (VREFA, VREFB)
3.4
Serial Data Input (SDI)
SDI is the SPI compatible serial data input.
VREFA and VREFB are DAC voltage reference inputs. The analog signal on these pins is utilized to set the reference voltage on the string DAC. The input signal can range from AVSS to VDD.
3.5
Latch DAC Input (LDAC)
3.9
Analog Ground (AVSS)
LDAC (the latch DAC syncronization input) transfers the input latch registers to the DAC registers (output latches) when low. Can also be tied low if transfer on the rising edge of CS is desired.
AVSS is the analog ground pin.
2004 Microchip Technology Inc.
DS21897A-page 15
MCP4921/4922
4.0 GENERAL OVERVIEW
INL < 0 111 110 101 Digital Input Code 100 011 010 001 000 INL < 0 DAC Output Ideal transfer function Actual transfer function The MCP492X devices are voltage output string DACs. These devices include input amplifiers, rail-to-rail output amplifiers, reference buffers, shutdown and resetmanagement circuitry. Serial communication conforms to the SPI protocol. The MCP492X operates from 2.7V to 5.5V supplies. The coding of these devices is straight binary and the ideal output voltage is given by Equation 4-1, where G is the selected gain (1x or 2x), DN represents the digital input value and n represents the number of bits of resolution (n = 12).
EQUATION 4-1:
LSB SIZE
V REF GD N VOUT = ------------------------n 2 1 LSB is the ideal voltage difference between two successive codes. Table 4-1 illustrates how to calculate LSB.
FIGURE 4-1: 4.0.2
INL Accuracy.
TABLE 4-1:
Device MCP492X MCP492X
LSB SIZES
VREF, GAIN External VREF, 1x External VREF, 2x LSB SIZE VREF/4096 2 VREF/4096
DNL ACCURACY
DNL error is the measure of variations in code widths from the ideal code width. A DNL error of zero would imply that every code is exactly 1 LSB wide.
4.0.1
INL ACCURACY
111 110 101 Digital Input Code 100 011 010 001 000 Narrow code < 1 LSB DAC Output Actual transfer function Ideal transfer function
INL error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point once offset and gain errors have been removed. These endpoints are from 0x000 to 0xFFF. Refer to Figure 4-1. Positive INL means transition(s) later than ideal. Negative INL means transition(s) earlier than ideal.
Wide code, > 1 LSB
FIGURE 4-2: 4.0.3
DNL Accuracy.
OFFSET ERROR
Offset error is the deviation from zero voltage output when the digital input code is zero.
4.0.4
GAIN ERROR
Gain error is the deviation from the ideal output, VREF- 1 LSB, excluding the effects of offset error.
DS21897A-page 16
2004 Microchip Technology Inc.
MCP4921/4922
4.1
4.1.1
Circuit Descriptions
OUTPUT AMPLIFIERS
The DACs' outputs are buffered with a low-power, precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section 1.0 "Electrical Characteristics" for range and load conditions. In addition to resistive load driving capability, the amplifier will also drive high capacitive loads without oscillation. The amplifiers' strong outputs allow VOUT to be used as a programmable voltage reference in a system. Selecting a gain of 2 reduces the bandwidth of the amplifier in Multiplying mode. Refer to Section 1.0 "Electrical Characteristics" for the Multiplying mode bandwidth for given load conditions.
If the power supply voltage is less than the POR threshold (VPOR = 2.0V, typical), the DACs will be held in their reset state. They will remain in that state until VDD > VPOR and a subsequent write command is received. Figure 4-3 shows a typical power supply transient pulse and the duration required to cause a reset to occur, as well as the relationship between the duration and trip voltage. A 0.1 F decoupling capacitor mounted as close as possible to the VDD pin provides additional transient immunity.
5V Supply Voltages VPOR VDD - VPOR Transient Duration
4.1.1.1
Programmable Gain Block
Transient Duration (s)
The rail-to-rail output amplifier has configurable gain allowing optimal full-scale outputs for differing voltage reference inputs. The output amplifier gain has two selections, a gain of 1 V/V (GA = 1) or a gain of 2 V/V (GA = 0). The output range is ideally 0.000V to 4095/4096 * VREF when G = 1, and 0.000 to 4095/4096 * VREF when G = 2. The default value for this bit is a gain of 2, yielding an ideal full-scale output of 0.000V to 4.096V when utilizing a 2.048V VREF. Note that the near rail-to-rail CMOS output buffer's ability to approach AVSS and VDD establish practical range limitations. The output swing specification in Section 1.0 "Electrical Characteristics" defines the range for a given load condition.
Time 10 8 6 4 2 0
Transients below the curve will NOT cause a reset
TA = +25C
Transients above the curve will cause a reset
1
2 3 4 VDD - VPOR (V)
5
4.1.2
VOLTAGE REFERENCE AMPLIFIERS
FIGURE 4-3: Response. 4.1.4
Typical Transient
The input buffer amplifiers for the MCP492X devices provide low offset voltage and low noise. A configuration bit for each DAC allows the VREF input to bypass the input buffer amplifiers, achieving a Buffered or Unbuffered mode. The default value for this bit is unbuffered. Buffered mode provides a very high input impedance, with only minor limitations on the input range and frequency response. Unbuffered mode provides a wide input range (0V to VDD), with a typical input impedance of 165 k w/7 pF.
SHUTDOWN MODE
4.1.3
POWER-ON RESET CIRCUIT
The Power-On Reset (POR) circuit ensures that the DACs power-up with SHDN = 0 (high-impedance). The devices will continue to have a high-impedance output until a valid write command is performed to either of the DAC registers and the LDAC pin meets the input low threshold.
Shutdown mode can be entered by using either hardware or software commands. The hardware pin (SHDN) is only available on the MCP4922. During Shutdown mode, the supply current is isolated from most of the internal circuitry. The serial interface remains active, thus allowing a write command to bring the device out of Shutdown mode. When the output amplifiers are shut down, the feedback resistance (typically 500 k) produces a high-impedance path to AVSS. The device will remain in Shutdown mode until the SHDN pin is brought high and a write command with SD = 1 is latched into the device. When a DAC is changed from Shutdown to Active mode, the output settling time takes < 10 s, but greater than the standard Active mode settling time (4.5 s).
2004 Microchip Technology Inc.
DS21897A-page 17
MCP4921/4922
5.0
5.1
SERIAL INTERFACE
Overview
5.2
Write Command
The MCP492X family is designed to interface directly with the Serial Peripheral Interface (SPI) port, available on many microcontrollers, and supports Mode 0,0 and Mode 1,1. Commands and data are sent to the device via the SDI pin, with data being clocked-in on the rising edge of SCK. The communications are unidirectional and, thus, data cannot be read out of the MCP492X. The CS pin must be held low for the duration of a write command. The write command consists of 16 bits and is used to configure the DAC's control and data latches. Register 5-1 details the input registers used to configure and load the DACA and DACB registers. Refer to Figure 1-1 and Section 1.0 "Electrical Characteristics" AC Electrical Characteristics table for detailed input and output timing specifications for both Mode 0,0 and Mode 1,1 operation.
The write command is initiated by driving the CS pin low, followed by clocking the four configuration bits and the 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to be latched into the selected DAC's input registers. The MCP492X utilizes a double-buffered latch structure to allow both DACA's and DACB's outputs to be syncronized with the LDAC pin, if desired. Upon the LDAC pin achieving a low state, the values held in the DAC's input registers are transferred into the DACs' output registers. The outputs will transition to the value and held in the DACX register. All writes to the MCP492X are 16-bit words. Any clocks past 16 will be ignored. The most significant four bits are configuration bits. The remaining 12 bits are data bits. No data can be transferred into the device with CS high. This transfer will only occur if 16 clocks have been transferred into the device. If the rising edge of CS occurs prior, shifting of data into the input registers will be aborted.
REGISTER 5-1:
Upper Half: W-x A/B bit 15 W-x BUF
WRITE COMMAND REGISTER
W-x GA W-0 SHDN W-x D11 W-x D10 W-x D9 W-x D8 bit 8 Lower Half: W-x D7 bit 7
W-x D6
W-x D5
W-x D4
W-x D3
W-x D2
W-x D1
W-x D0 bit 0
bit 15
A/B: DACA or DACB Select bit 1 = Write to DACB 0 = Write to DACA
1= 0=
bit 14
BUF: VREF Input Buffer Control bit Buffered Unbuffered
bit 13
GA: Output Gain Select bit 1 = 1x (VOUT = VREF * D/4096) 0 = 2x (VOUT = 2 * VREF * D/4096) SHDN: Output Power Down Control bit 1 = Output Power Down Control bit 0 = Output buffer disabled, Output is high impedance D11:D0: DAC Data bits 12 bit number "D" which sets the output value. Contains a value between 0 and 4095.
bit 12
bit 11-0
Legend R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown
DS21897A-page 18
2004 Microchip Technology Inc.
MCP4921/4922
CS 0 SCK config bits SDI 12 data bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (mode 1,1) (mode 0,0)
A/B BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LDAC
VOUT
FIGURE 5-1:
Write Command.
2004 Microchip Technology Inc.
DS21897A-page 19
MCP4921/4922
6.0
Note:
TYPICAL APPLICATIONS
At the time of this data sheet's release, circuit examples had not completed testing. Your results may vary. VDD VDD 0.1 F 0.1 F VREFA CS1 VDD
The MCP492X devices are general purpose DACs intended to be used in applications where a precision, low-power DAC with moderate bandwidth is required. Applications generally suited for the MCP492X devices include: * * * * * Set Point or Offset Trimming Sensor Calibration Digitally-Controlled Multiplier/Divider Portable Instrumentation (Battery Powered) Motor Feedback Loop Control 0.1 F
MCP492X
VOUTA VREFB VOUTB VREFA VOUTA VREFB VOUTB
MCP492X
SDI
AVSS
SDO SCK LDAC CS0
6.1
Digital Interface
The MCP492X utilizes a 3-wire syncronous serial protocol to transfer the DACs' setup and output values from the digital source. The serial protocol can be interfaced to SPITM or Microwire peripherals common on many microcontrollers, including Microchip's PICmicro(R) MCUs & dsPICTM DSC family of microcontrollers. In addition to the three serial connections (CS, SCK and SDI), the LDAC signal syncronizes when the serial settings are latched into the DAC's output from the serial input latch. Figure 6-1 illustrates the required connections. Note that LDAC is active-low. If desired, this input can be tied low to reduce the required connections from 4 to 3. Write commands will be latched directly into the output latch when a valid 16 clock transmission has been received and CS has been raised.
AVSS
AVSS
FIGURE 6-1: Diagram.
Typical Connection
6.3
Layout Considerations
6.2
Power Supply Considerations
The typical application will require a by-pass capacitor in order to filter high-frequency noise. The noise can be induced onto the power supply's traces or as a result of changes on the DAC's output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 6-1 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close to the device power pin (VDD) as possible (within 4 mm). The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, AVDD and AVSS should reside on the analog plane.
Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP492X's performance. Careful board layout will minimize these effects and increase the signal-to-noise ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. Breadboards and wire-wrapped boards are not recommended if low noise is desired.
DS21897A-page 20
2004 Microchip Technology Inc.
PICmicro(R) Microcontroller
SDI
MCP4921/4922
6.4 Single-Supply Operation
6.4.1.1 Decreasing The Output Step Size
The MCP492X is a rail-to-rail (R-R) input and output DAC designed to operate with a VDD range of 2.7V to 5.5V. Its output amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of an external buffer for most applications. If the output range is reduced relative to AVSS, simply reducing VREF will reduce the magnitude of each output step. If the application is calibrating the threshold of a diode, transistor or resistor tied to AVSS or VREF, a theshold range of 0.8V may be desired to provide 200 V resolution. Two common methods to achieve a 0.8V range is to either reduce VREF to 0.82V or use a voltage divider on the DAC's output. If a VREF is available with the desired output value, using that VREF is an option. Occasionally, when using a low-voltage VREF, the noise floor causes SNR error that is intolerable. The voltage divider method provides some advantages when VREF needs to be very low or when the desired output voltage is not available. In this case, a larger value VREF is used while two resistors scale the output range down to the precise desired level. Using a common VREF output has availability and cost advantages. Example 6-1 illustrates this concept. Note that the voltage divider can be connected to AVSS or VREF, depending on the application's requirements. The MCP492X's low, 0.75 (max.) DNL performance is critical to meeting calibration accuracy in production. VDD
6.4.1
DC SET POINT OR CALIBRATION
A common application for a DAC with the MCP492X's performance is digitally-controlled set points and/or calibration of variable parameters, such as sensor offset or slope. 12-bit resolution provides 4096 output steps. If a 4.096V VREF is provided, an LSB would represent 1 mV of resolution. If a smaller output step size is desired, the output range would need to be reduced.
Rsense VREF VDD VOUT R1
VCC+
Comparator
Vtrip VCC-
MCP492X
R2 SPITM 3 D V OUT = V REF G ------12 2 R2 V trip = V OUT ------------------ R1 + R 2
0.1 uF
G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096)
EXAMPLE 6-1:
Set Point or Threshold Calibration.
2004 Microchip Technology Inc.
DS21897A-page 21
MCP4921/4922
6.4.1.2 Building a "Window" DAC
When calibrating a set point or threshold of a sensor, rarely does the sensor utilize the entire output range of the DAC. If the LSB size is adequate to meet the application's accuracy needs, then the resolution is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. If the threshold is not near VREF or AVSS, then creating a "window" around the threshold has several advantages. One simple method to create this "window" is to use a voltage divider network with a pull-up and pulldown resistor. Example 6-2 and Example 6-4 illustrates this concept. The MCP492X's low, 0.75 (max.) DNL performance is critical to meet calibration accuracy in production.
VCC+ VREF VDD VOUT R3 R1
Rsense
VCC+
Comparator Vtrip 0.1 F VCCVCC-
MCP492X
R2 SPITM 3
D V OUT = V REF G ------12 2 R 2 R3 R 23 = -----------------R2 + R 3 V 23 ( V CC+ R 2 ) + ( V CC- R 3 ) = ----------------------------------------------------R 2 + R3
G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096) R1 VOUT VO R23 V23
Thevenin Equivalent
V OUT R23 + V 23 R 1 V trip = ------------------------------------------R 2 + R 23
EXAMPLE 6-2:
Single-Supply "Window" DAC.
DS21897A-page 22
2004 Microchip Technology Inc.
MCP4921/4922
6.5 Bipolar Operation
Bipolar operation is achievable using the MCP492X by using an external operational amplifier (op amp). This configuration is desirable due to the wide variety and availability of op amps. This allows a general purpose DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. Example 6-3 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VREF, instead of AVSS, if a higher offset is desired. Note that a pull-up to VREF could be used, instead of R4, if a higher offset is desired.
R2 VREF VREF VDD VOUT R3 R1 VIN+ VCC- R4 SPITM 3 D VOUT = VREF G ------12 2 V OUT R 4 VIN+ = ------------------R3 + R4 R2 R2 VO = VIN+ 1 + ----- - V REF ----- R 1 R1 0.1 F VCC+ VO
MCP492X
G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096)
EXAMPLE 6-3: 6.5.1
Digitally-Controlled Bipolar Voltage Source.
4. Next, solve for R3 and R4 by setting the DAC to 4096, knowing that the output needs to be +2.05V. R4 2.05V + 0.5V REF 2 ---------------------- = ----------------------------------------- = -1.5VREF ( R3 + R 4 ) 3 If R4 = 20 k, then R3 = 10 k
DESIGN A BIPOLAR DAC USING EXAMPLE 6-3
An output step magnitude of 1 mV with an output range of 2.05V is desired for a particular application. 1. 2. Calculate the range: +2.05V - (-2.05V) = 4.1V. Calculate the resolution needed: 4.1V/1 mV = 4100 Since 212 = 4096, 12-bit resolution is desired. 3. The amplifier gain (R2/R1), multiplied by VREF, must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R1+R2), the VREF source needs to be determined first. If a VREF of 4.1V is used, solve for the gain by setting the DAC to 0, knowing that the output needs to be -2.05V. The equation can be simplified to: - R2 - 2.05 - 2.05 -------- = ------------ = -----------R1 V REF 4.1 R2 1 ----- = -R1 2
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
2004 Microchip Technology Inc.
DS21897A-page 23
MCP4921/4922
6.6 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC
This circuit is typically used in Multiplier mode and is ideal for linearizing a sensor whose slope and offset varies. Refer to Section 6.9 "Using Multiplier Mode" for more information on Multiplier mode. The equation to design a bipolar "window" DAC would be utilized if R3, R4 and R5 are populated.
In some applications, precision digital control of the output range is desirable. Example 6-4 illustrates how to use the MCP4922 to achieve this in a bipolar or single-supply application.
R2 VREFA VDD VOUTA R1 VCC+ R5
VCC+
MCP492X
VREFB VDD DACA (Gain Adjust) VOUTB R3 VO
MCP492X
SPITM 3
DACB (Offset Adjust)
R4 VCC-
0.1uF
VCC-
DB VOUTB = ( V REFB G B ) ------12 2 V OUTB R 4 + VCC- R 3 V IN+ = ----------------------------------------------R 3 + R4 R2 R2 VO = V IN+ 1 + ----- - V OUTA ----- R 1 R1 Offset Adjust Gain Adjust
DA V OUTA = ( VREFA G A ) ------12 2 AVSS = GND G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096)
Bipolar "Window" DAC using R4 and R5 Thevenin Equivalent V CC+ R 4 + VCC- R5 V45 = ------------------------------------------R 4 + R5 V OUTB R45 + V 45 R 3 V IN+ = ---------------------------------------------R 3 + R 45 R4 R5 R 45 = -----------------R4 + R5 R2 R2 V O = VIN+ 1 + ----- - V OUTA ----- R 1 R1 Offset Adjust Gain Adjust
EXAMPLE 6-4:
Bipolar Voltage Source With Selectable Gain and Offset.
DS21897A-page 24
2004 Microchip Technology Inc.
MCP4921/4922
6.7 Designing A Double-Precision DAC Using A Dual DAC
1. Calculate the resolution needed: 4.1V/1uV = 4.1e06. Since 222 = 4.2e06, 22-bit resolution is desired. Since DNL = 0.75 LSB, this design can be attempted with the MCP492X. Since DACB`s VOUTB has a resolution of 1 mV, its output only needs to be "pulled" 1/1000 to meet the 1 V target. Dividing VOUTA by 1000 would allow the application to compensate for DACB`s DNL error. If R2 is 100, then R1 needs to be 100 k. The resulting transfer function is not perfectly linear, as shown in the equation of Example 6-5.
Example 6-5 illustrates how to design a single-supply voltage output capable of up to 24-bit resolution from a dual 12-bit DAC. This design is simply a voltage divider with a buffered output. As an example, if a similar application to the one developed in Section 6.5.1 "Design a bipolar dac using Example 6-3" required a resolution of 1 V instead of 1 mV and a range of 0V to 4.1V, then 12-bit resolution would not be adequate.
2.
3. 4.
VREF
VDD DACA (Fine Adjust) VOUTA R1 >> R2 VOUTB R2 0.1 F DACB (Course Adjust)
VCC+ VO R1
MCP492X
VDD
MCP492X
SPITM 3
VCC-
DA V OUTA = V REFA G A ------12 2 VOUTA R 2 + VOUTB R 1 V O = ----------------------------------------------------R 1 + R2
DB V OUTB = VREFB G B ------12 2
G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096)
EXAMPLE 6-5:
Simple, Double-Precision DAC.
2004 Microchip Technology Inc.
DS21897A-page 25
MCP4921/4922
6.8 Building A Programmable Current Source 6.9 Using Multiplier Mode
The MCP492X is ideally suited for use as a multiplier/ divider in a signal chain. Common applications include: precision programmable gain/attenuator amplifiers and loop controls (motor feedback). The wide input range (0V - VDD) is an Unbuffered mode and near R-R range in Buffered mode: the > 400 kHz bandwidth, selectible 1x/2x gain and its low power consumption give maximum flexibility to meet the application's needs. To configure the MCP492X in Multiplier mode, connect the input signal to VREF and serially configure the DAC's input buffer, gain and output value. The DAC's output can utilize any of Examples 6-1 to 6-6, depending on the application requirements. Example 6-7 is an illustration of how the DAC can operate in a motor control feedback loop. If the Gain Select bit is configured for 1x mode (GA = 1), the resulting input signal will be attenuated by D/4096. If the Gain Select bit is configured for 2x mode (GA = 0), codes < 2048 attenuate the signal, while codes > 2048 gain the signal. VOUT = VIN (D/2048). IL VCC- Ib 3 D V OUT = V REF G ------12 2 IL I b = --- V OUT I L = -------------- x ----------Rsense + 1 G = Gain select (1x or 2x) D = Digital value of DAC (0 - 4096) VREF SPITM VDD ZFB VOUT VCC+ + Rsense A 12-bit DAC provides significantly more gain/attenuation resolution when compared to typical Programmable Gain Amplifiers. Adding an op amp to buffer the output, as illustrated in Examples 6-2 to 6-6, extends the output range and power to meet the precise needs of the application. VRPM_SET VRPM
Example 6-6 illustrates a variation on a voltage follower design where a sense resistor is used to convert the DAC's voltage output into a digitally-selectable current source. Adding the resistor network from Example 6-2 would be advantageous in this application. The smaller Rsense is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled with. The voltage divider, or "window", DAC configuration would allow the range to be reduced, thus increasing resolution around the range of interest. When working with very small sensor voltages, plan on eliminating the amplifier's offset error by storing the DAC's setting under known sensor conditions.
VREF
VDD VOUT VCC+ LOAD
MCP492X
SPITM
MCP492X
EXAMPLE 6-6:
Digitally-Controlled Current Source.
3
- VCC- Rsense
EXAMPLE 6-7:
Multiplier Mode.
DS21897A-page 26
2004 Microchip Technology Inc.
MCP4921/4922
7.0
7.1
DEVELOPMENT SUPPORT
Evaluation & Demonstration Boards 7.2 Application Notes and Tech Briefs
The Mixed Signal PICtailTM Board supports the MCP492X family of devices. Please refer to www.microchip.com for further information on this products capabilities and availability.
Application notes illustrating the performace and implementation of the MCP492X are planned but currently not released. Please refer to www.microchip.com for further information.
2004 Microchip Technology Inc.
DS21897A-page 27
MCP4921/4922
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
8-Lead MSOP XXXXXX YWWNNN Example: 4921E 412256
8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW
Example: MCP4921 E/P256 0412
8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN
Example: MCP4921 E/SN0412 256
Legend:
XX...X YY WW NNN
Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
DS21897A-page 28
2004 Microchip Technology Inc.
MCP4921/4922
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP4922) Example:
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
MCP4922E/P 0412256
14-Lead SOIC (150 mil) (MCP4922)
Example:
XXXXXXXXXX XXXXXXXXXX YYWWNNN
MCP4922E/SL 0412256
14-Lead TSSOP (MCP4922)
Example:
XXXXXX YYWW NNN
4922E/ST 0412 256
2004 Microchip Technology Inc.
DS21897A-page 29
MCP4921/4922
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E E1
p D 2 B n 1
A c A1 (F)
A2
L
8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness A1 .000 .006 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF 0 8 Foot Angle c Lead Thickness .003 .006 .009 Lead Width B .009 .012 .016 5 5 15 Mold Draft Angle Top 5 5 15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
Units Dimension Limits n p
MIN
INCHES NOM
MAX
MIN
MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 -
MAX
1.10 0.95 0.15
0.80 8 0.23 0.40 15 15
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21897A-page 30
2004 Microchip Technology Inc.
MCP4921/4922
8-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D 2 n 1 E
A
A2
c
L A1
eB
B1 p B
Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
MIN
INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10
MAX
MIN
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
2004 Microchip Technology Inc.
DS21897A-page 31
MCP4921/4922
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC)
E E1
p
D 2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
DS21897A-page 32
2004 Microchip Technology Inc.
MCP4921/4922
14-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n 1
E A A2
c eB A1 B1 B p
L
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005
Units Dimension Limits n p
MIN
INCHES* NOM 14 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15
2004 Microchip Technology Inc.
DS21897A-page 33
MCP4921/4922
14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC)
E E1
p
D
2 B n 1 h 45 c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0
INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15
MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065
DS21897A-page 34
2004 Microchip Technology Inc.
MCP4921/4922
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP)
E E1 p
D
2 n B 1
A c
L A1 A2
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1
MIN
INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5
MAX
MIN
.033 .002 .246 .169 .193 .020 0 .004 .007 0 0
.043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10
MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087
2004 Microchip Technology Inc.
DS21897A-page 35
MCP4921/4922
NOTES:
DS21897A-page 36
2004 Microchip Technology Inc.
MCP4921/4922
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples:
a) MCP4921T-E/SN: Tape and Reel Extended Temperature, 8LD SOIC package. MCP4921T-E/MS: Tape and Reel Extended Temperature, 8LD MSOP package. MCP4921-E/SN: Extended Temperature, 8LD SOIC package. MCP4921-E/MS: Extended Temperature, 8LD MSOP package. MCP4921-E/P: Extended Temperature, 8LD PDIP package. MCP4922T-E/SL: Tape and Reel Extended Temperature, 14LD SOIC package. Tape and Reel Extended Temperature, 14LD TSSOP package. Extended Temperature, 14LD PDIP package. Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD TSSOP package.
b) Device: MCP4921: MCP4921T: MCP4922: MCP4922T: 12-Bit DAC with SPI Interface 12-Bit DAC with SPI Interface (Tape and Reel) (SOIC, MSOP) 12-Bit DAC with SPI Interface 12-Bit DAC with SPI Interface (Tape and Reel) (SOIC, MSOP)
c) d) e)
Temperature Range:
E
= -40C to +125C
a)
Package:
MS P SN SL ST
= = = = =
Plastic MSOP, 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC, (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Plastic TSSOP (4.4mm Body), 14-lead
b)
MCP4922T-E/ST:
c) d) e)
MCP4922-E/P: MCP4922-E/SL: MCP4922-E/ST:
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21897A-page 37
MCP4921/4922
NOTES:
DS21897A-page 38
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21897A-page 39
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: www.microchip.com
China - Beijing
Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. Beijing, 100027, China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934
Singapore
200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
China - Chengdu
Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Atlanta
3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307
Taiwan
Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4818 Fax: 886-7-536-4803
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Fuzhou
Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
Taiwan
Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
EUROPE
Austria
Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
China - Shanghai
Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Denmark
Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393
Kokomo
2767 S. Albright Road Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
China - Shunde
Room 401, Hongjian Building, No. 2 Fengxiangnan Road, Ronggui Town, Shunde District, Foshan City, Guangdong 528303, China Tel: 86-757-28395507 Fax: 86-757-28395571
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
China - Qingdao
Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Germany
Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
San Jose
1300 Terra Bella Avenue Mountain View, CA 94043 Tel: 650-215-1444 Fax: 650-961-0286
India
Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-22290061 Fax: 91-80-22290062
Italy
Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
Japan
Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Netherlands
Waegenburghtplein 4 NL-5152 JR, Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340
ASIA/PACIFIC
Australia
Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
United Kingdom
505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820
05/28/04
DS21897A-page 40
2004 Microchip Technology Inc.

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